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VHDL-based FPGA development for the micro-line C6412Compact
DSP / FPGA platform. |
enables development of customized FPGA designs | |
contains VHDL framework for completely new designs | |
contains micro-line busmaster FPGA design as starting point for new designs | |
IP cores for operation of the IEEE1394 chipsets included | |
UART IP core included | |
configurable EMIF interface included as source code | |
documentation of all components included | |
Timing simulation available as an option |
The FPGA Development Package
Spartan-3 FPGA Technology
A Rich Set of Resources
Different clock sources eliminate the need for external clock
oscillators. Available are:
Up to 218 FPGA I/O connections to the micro-line connectors gives enough I/O capability for implementing multiple external interfaces. Most of these I/O resources can be used freely for own FPGA designs. The block diagram below shows the wiring of the FPGA for a C6412Compact in standard configuration (HPI16 & Ethernet).
micro-line Busmaster BSP FPGA Design Included
Alternatives to the micro-line Busmaster BSP
Development Tools |
Technical Data |
The FPGA Development Package includes: |
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micro-line busmaster BSP |
The default FPGA for the micro-line C6412Compact, as included in
the software development kits. Implements access to the IEEE1394 chipsets, a peripheral interface, an auxiliary UART, configurable clock outputs and programmable LED control. Provided as an ISE project, separately for each device. |
VHDL framework |
Defines all available FPGA connections Available for each hardware configuration of the C6412Compact Synthesizable VHDL top-level entity |
IEEE1394 IP cores |
Common IP core for FIFO buffered, 64-bit wide access to the
register interface of both IEEE1394 chipsets. FIFO buffered, 64-bit wide access to streaming data over a dedicated interface of the IEEE 1394 chipsets, separate for each chipset and each transfer direction. |
UART IP core |
FIFO buffered UART IP core with programmable baud rates. |
Simulation suport |
Recorded simulation sessions included for reference. Timing simulation with ModelSim available as an option |
Documentation |
FPGA Programming Guide Streaming cores user's guide UART IP core user's guide |
For more information about the |
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