The
FPGA Development Package
The FPGA development package gives the user the
possibility to add virtually any kind of hardware to the
C641xCPU series. Interfaces not supported by the C641xCPU can be
added by an appropriate FPGA design. Communication between DSP
and external hardware can be optimized to perfectly fit the
connected components. Data transfer overhead between DSP and
FPGA can be minimized using different methods, such as a FIFO
buffer or direct SDRAM access by the FPGA. High speed signal
processing, such as decimation filters, etc. can be moved from
DSP software to the FPGA, relieving the DSP.
Spartan-3E FPGA Technology
The Spartan-3E devices used in the C641xCPU are
successors of the earlier, successful Spartan-IIE family,
equipped with more logic resources, more memory capacity and
improved clock management. Some key features of these devices (shown
for an XC3S1600E device) are:
- 81 Kbyte block RAM
- 622+ Mbps data rate per I/O
- 8 Digital Clock Managers (DCM) for clock de-skew, frequency synthesis, etc.
- 36 dedicated 18x18 hardware multipliers
A Rich Set of Resources
On the C641xCPU, the user benefits from a rich set of
resources. Connection to the DSP external memory interface
(EMIF) provides the link between hardware data processing in the
FPGA and software data processing in the DSP. Further, the FPGA
can arbitrate for the EMIF and access on-board SDRAM
autonomously. Three different clock sources eliminate the need
for external clock oscillators. The large number of 102 FPGA I/O
connections to the micro-line connectors gives enough I/O
capability for implementing multiple external interfaces. Most
of these I/O resources can be used freely for own FPGA
designs.
micro-line
Busmaster
BSP FPGA Design Included
The included FPGA design of the micro-line busmaster
provides a well qualified starting point for own designs. This
design is provided as development project, including VHDL source
code and the UART IP core. Reliability of this design is
guaranteed by timing constraints and can further be verified by
timing simulation. A previously recorded simulation run of the
micro-line busmaster FPGA design serves as a reference. Detailed
step-by-step procedures show different aproaches to own
designs.
Development Tools
The default development
environment is Xilinx ISE. It provides the complete design process from
code entry to programming file generation and FPGA configuration. The
Spartan-3E devices are completely supported by the free WebPack version
of Xilinx ISE. As an alternative, Xilinx ISE Foundation can also be
used. For timing simulation of smaller designs, the starter version of
ModelSim XE can be used. For simulation of larger and complex designs
the full version of ModelSim XE is recommended. After development has
finished, the FPGA can be configured by different methods:
- direct configuration over JTAG
- automatic configuration on startup by the C641xCPU's Flash File System
- application software controlled configuration from flash memory or RAM
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