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VHDL-based FPGA development for the micro-line C6713Compact-2
DSP / FPGA platform. |
Enables development of customized FPGA designs | |
Contains VHDL framework for completely new designs | |
Contains micro-line busmaster FPGA design as starting point for new designs | |
IP core for operation of the IEEE1394 chipset included | |
IP core for DDR3 memory access included | |
Documentation of all components included |
The FPGA Development Package
Spartan-6 FPGA Technology
A Rich Set of Resources Boards with LX75 FPGA or higher have access to 256 Mbytes of dedicated DDR3-800 memory. A predefined core from Orsys
provides the necessary infrastructure and implements a single,
32-bit wide bi-directional DDR3 memory port for FPGA-designers. Different clock sources eliminate the need for external clock oscillators. Available are:
Up to 160 FPGA I/O lines to the micro-line connectors provide enough I/O resources for implementing multiple external interfaces. Most of these I/O connections can be used freely by the customer. The block diagram below shows the wiring of the C6713Compact-2 FPGA.
micro-line Busmaster BSP FPGA Design Included
Alternatives to the micro-line Busmaster BSP
Development Tools |
Technical Data |
The FPGA Development Package includes: |
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micro-line busmaster BSP |
The default FPGA for the micro-line C6713Compact-2, as included in
the software development kits. Implements access to the data mover port of the IEEE1394 chipset, a peripheral interface, configurable EMIF clock output and user LED control. Provided as an ISE project, separately for each device. Timing simulation provided by Isim scripts. |
VHDL framework |
Defines all available FPGA connections Synthesizable VHDL top-level entity |
IEEE1394 IP core |
IP core for FIFO buffered, 32-bit wide access to streaming data
over a dedicated interface of the IEEE 1394 chipset (data mover
port) |
DDR access core |
MCB core implementation, customized for C6713Compact-2. 400MHz operation (DDR3-800) Single-port, 32-bit wide, bi-directional interface. |
Simulation support |
Scripts for timing simulation of the micro-line busmaster BSP Simulation model for asynchronous DSP EMIF Simulation model for IEEE1394 chipset's data mover port Simulation model for a micro-line peripheral component |
Documentation |
FPGA Programming Guide Streaming IP core user's guide |
For more information about the |
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